Aditya Venkatesh's Personal Website

RISC, or Reduced Instruction Set Computer, is a type of processor architecture that uses simplified CPU instructions, making them faster and more granular. In this project, I built a 16-bit processor with SystemVerilog and ran it on a Spartan-7 FPGA. The processor was built to follow a subset of the SLC-3 RISC ISA.

Hardware Description Language (HDL), like SystemVerilog, allows for the creation of programmable hardware functions on FPGAs, which I used to create efficient modules that functioned as core processor components, such as the ALU and control unit.

Along with the processor, I implemented the memory subsystem for the processor, backed by MMIO. The MMIO used was the on-chip BRAM of the FPGA, which proved sufficient for the project. Connected via the main bus, read and write access was controlled via the various control registers of the processor. Back to the processor, I implemented modules including the ALU, register file, PC unit, and the control unit.

The control unit, particularly, was rather complex, with its finite state machine spanning several dozen nodes. It was a challenge to extract a particular subset of the ISA while still maintaining desired functionality.